1. Field of Invention
The present invention relates to a delay line. More particularly, the present invention relates to a delay line that transmits the first level stage by stage according to a delay time decided by the sensing period, and reset to the second level when the sensing period is finished, and an analog-to-digital converting device and a load-sensing circuit using the same.
2. Description of Related Art
Signal converting circuits are essential to electronic products that require data communication and image processing, even through we are now entering the system-on-chip (SOC) era. FIG. 1 is a circuit diagram of a common delay circuit. If a conventional delay circuit is applied to a signal converting circuit, as common delay circuits mainly adopt the voltage-control mode, that is, the input voltage Vin to be converted into digital codes is taken as the supply voltage in the delay circuit, thus the delay difference in signal transmission will occur. However, as the voltage swing of the output signal of each of the delay cells is 0˜Vin, logic operation errors may occur at the back end decoder due to the difference between the voltage and the supply voltage of the decoder. In order to solve the problem, a level shifter is added to mediate and convert the voltage levels of the signals of the delay circuit and the decoder to be the same, such that the correct logic operation can be performed. If the error value of the trigger time of the delay signal to be processed is quite critical, the level shifter should be fast. Thus, the signal processing becomes complicated, and the power consumption increases as well.
Furthermore, in order to improve the service lifetime of the product and the battery, the power consumption of the converting circuit and whether quick sensing and code conversion can be achieved become very important indices. FIG. 2 is a circuit diagram of a conventional signal converting circuit. A conventional signal converting circuit (e.g., an analog-to-digital converter) usually uses a large quantity of comparators CP and resistors R. A plurality of resistors R is connected in series to form a voltage divider, so as to further provide reference voltages at different levels to corresponding comparators CP. Each of the comparators compares the input voltage Vin that is to be converted into digital codes and the corresponding reference voltage, and the comparators CP thus output digital codes corresponding to the input voltage Vin. However, the number of comparators CP required will increase when the bit number of the digital codes to be generated is increased, thus aggravating the power consumption problem.